Typically, it is extremely difficult to achieve a high-speed high-resolution AD converter (for example, with a sampling speed of larger than several hundreds [MHz] and a resolution of larger than 10 [bit]). Therefore, this converter cannot be achieved, or this will be high-priced even if achieved. A low-price converter is obtained by sacrificing one of the required performances. That is, it is provided with high-speed and low-resolution (for example, with a sampling speed of larger than several hundreds [MHz] and a resolution of several bits) or with low-speed and high-resolution (for example, with a sampling speed of several tens [MHz] and a resolution of larger than 10 [bit]). As a technology of combining together a plurality of the latter low-speed high-resolution AD converters to thereby effectively achieve a high-speed high-resolution AD converter, there is a time-interleaved AD converter.
FIG. 1 shows an example of the basic configuration of the time-interleaved AD converter, showing a case where four low-speed high-resolution AD converters (ADC 0 to ADC 3) with a resolution of K1[bit] are combined together (M=4). FIG. 2 is a timing diagram of FIG. 1.
In principle, through frequency dividing of a clock CLK of 4×FS [Hz], FS[Hz], four-phase clocks CLK 0 to CLK 3 are created with a phase shift of 1/FS/4 [sec] in the FS [Hz].In the ADC 0 to ADC 3, by converting an analog input signal by use of these clocks and then cyclically multiplexing the converted signals SIG 0 to SIG 3, a digital signal x[n] can be obtained which is equivalent to that obtained by a high-speed high-resolution AD converter with a sampling speed of 4×FS [Hz] and a resolution of K1[bit].
However, in fact, due to influence of the presence of nonideality or variation, such as DC offset, conversion gain error, sampling timing error, and a frequency characteristic, each of the AD converters suffers from a problem that the x[n] has spurious.
To solve this problem, various compensation methods have been suggested. Now, considering the installation ease and usability, neither a method which requires an additional particular analog circuit nor a method which requires a special training signal, but a method is suitable by which compensation is made by using only a multipurpose component and digital signal processing based on only a signal desired to be converted. JP-A No. 2004-165988 “Digital Quadrature Demodulator” describes one example of such a method.
In the JP-A No. 2004-165988, the number of low-speed high-resolution AD converters is limited to 2; thus, speeding up effect is just twice the effect provided by a low-speed high-resolution AD converter alone. JP-A No.2004-328436, “A/D Converter” describes one example of a conventional technology in which the number of low-speed high-resolution AD converters can be increased.
In JP-A No. 2004-328436, “A/D Converter”, linear filter operation is applied for compensation; thus, the compensation can be made even when each low-speed high-resolution AD converter has a frequency response.